By Manuel F. M. Barros, Jorge M. C. Guilherme, Nuno C. G. Horta (auth.)
The microelectronics industry tendencies current an ever-increasing point of complexity with specified emphasis at the creation of advanced mixed-signal systems-on-chip. Strict monetary and layout pressures have pushed the improvement of recent ways to automate the analog layout approach. although, and regardless of a few major learn efforts, the basic act of layout on the transistor point continues to be played through the trial and mistake interplay among the clothier and the simulator.
This e-book provides a brand new layout automation technique according to a changed genetic set of rules kernel, with the intention to increase potency at the analog IC layout cycle. The proposed strategy combines a strong optimization with nook research, computing device studying concepts and allotted processing strength capable of care for multi-objective and limited optimization difficulties. The ensuing optimization instrument and the development in layout productiveness is established for the layout of CMOS operational amplifiers.
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Extra info for Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques
Interactive Design. The tool optionally produces intermediate performance reports (in the form of text or graphics) throughout the design execution time to inform the IC designer on the optimization progress. , the dimension of a transistor or the redefinition of some design bias. Bookkeeping Facilities. ), different performance measurements, different design parameters, different components, different topologies, and so on. Encapsulate Details. Some tools interact with external programs and so it makes sense that the interface with these additional tools can be made in an automatically way hiding unused options.
In: Proc. 22nd ACM/IEEE Conference on Design Automation, pp. : A novel analog layout synthesis tool. In: Proc. IEEE Int. Symposium on Circuits and Systems, vol. 5, pp. : LAYGEN – An evolutionary approach to automatic analog IC layout generation. In: Proc. IEEE Conf. : LAYGEN – Automatic layout generation of analog ICs from hierarchical template descriptions. In: Proc. IEEE Ph. D. Research in Microelectronics and Electronics, pp. 213–216 (2006)  Cadence Inc. : Analog circuits optimization based on evolutionary computation techniques.
Distributed processing and robust design. SPICE/ HSPICE engines + “feasibility models” Circuit 2006 Simulator +SVM =Means “not implemented in tool” = Means “implemented in tool” Encapsulate inhouse environment (AIDA). Can use dynamic model generation. 20 min. 40GHz PC) MATLAB performance parameter macro-models MIT GAlib 2004 NN VEMURI  31 Par. 21 devices 41 const. Explores sampling methodologies to improve model quality. 9 s of SunBlade 100 execution time to generate the model training samples(3125).